
dijkstra:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400540 <_init>:
  400540:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400544:	910003fd 	mov	x29, sp
  400548:	9400003c 	bl	400638 <call_weak_fn>
  40054c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400550:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400560 <.plt>:
  400560:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400564:	90000090 	adrp	x16, 410000 <__FRAME_END__+0xf2fc>
  400568:	f947fe11 	ldr	x17, [x16, #4088]
  40056c:	913fe210 	add	x16, x16, #0xff8
  400570:	d61f0220 	br	x17
  400574:	d503201f 	nop
  400578:	d503201f 	nop
  40057c:	d503201f 	nop

0000000000400580 <__libc_start_main@plt>:
  400580:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400584:	f9400211 	ldr	x17, [x16]
  400588:	91000210 	add	x16, x16, #0x0
  40058c:	d61f0220 	br	x17

0000000000400590 <__gmon_start__@plt>:
  400590:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  400594:	f9400611 	ldr	x17, [x16, #8]
  400598:	91002210 	add	x16, x16, #0x8
  40059c:	d61f0220 	br	x17

00000000004005a0 <abort@plt>:
  4005a0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4005a4:	f9400a11 	ldr	x17, [x16, #16]
  4005a8:	91004210 	add	x16, x16, #0x10
  4005ac:	d61f0220 	br	x17

00000000004005b0 <puts@plt>:
  4005b0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4005b4:	f9400e11 	ldr	x17, [x16, #24]
  4005b8:	91006210 	add	x16, x16, #0x18
  4005bc:	d61f0220 	br	x17

00000000004005c0 <__isoc99_scanf@plt>:
  4005c0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4005c4:	f9401211 	ldr	x17, [x16, #32]
  4005c8:	91008210 	add	x16, x16, #0x20
  4005cc:	d61f0220 	br	x17

00000000004005d0 <printf@plt>:
  4005d0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4005d4:	f9401611 	ldr	x17, [x16, #40]
  4005d8:	9100a210 	add	x16, x16, #0x28
  4005dc:	d61f0220 	br	x17

00000000004005e0 <putchar@plt>:
  4005e0:	b0000090 	adrp	x16, 411000 <__libc_start_main@GLIBC_2.17>
  4005e4:	f9401a11 	ldr	x17, [x16, #48]
  4005e8:	9100c210 	add	x16, x16, #0x30
  4005ec:	d61f0220 	br	x17

Disassembly of section .text:

00000000004005f0 <_start>:
  4005f0:	d280001d 	mov	x29, #0x0                   	// #0
  4005f4:	d280001e 	mov	x30, #0x0                   	// #0
  4005f8:	aa0003e5 	mov	x5, x0
  4005fc:	f94003e1 	ldr	x1, [sp]
  400600:	910023e2 	add	x2, sp, #0x8
  400604:	910003e6 	mov	x6, sp
  400608:	580000c0 	ldr	x0, 400620 <_start+0x30>
  40060c:	580000e3 	ldr	x3, 400628 <_start+0x38>
  400610:	58000104 	ldr	x4, 400630 <_start+0x40>
  400614:	97ffffdb 	bl	400580 <__libc_start_main@plt>
  400618:	97ffffe2 	bl	4005a0 <abort@plt>
  40061c:	00000000 	.inst	0x00000000 ; undefined
  400620:	00400a90 	.word	0x00400a90
  400624:	00000000 	.word	0x00000000
  400628:	00400bf0 	.word	0x00400bf0
  40062c:	00000000 	.word	0x00000000
  400630:	00400c70 	.word	0x00400c70
  400634:	00000000 	.word	0x00000000

0000000000400638 <call_weak_fn>:
  400638:	90000080 	adrp	x0, 410000 <__FRAME_END__+0xf2fc>
  40063c:	f947f000 	ldr	x0, [x0, #4064]
  400640:	b4000040 	cbz	x0, 400648 <call_weak_fn+0x10>
  400644:	17ffffd3 	b	400590 <__gmon_start__@plt>
  400648:	d65f03c0 	ret
  40064c:	00000000 	.inst	0x00000000 ; undefined

0000000000400650 <deregister_tm_clones>:
  400650:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400654:	91012000 	add	x0, x0, #0x48
  400658:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40065c:	91012021 	add	x1, x1, #0x48
  400660:	eb00003f 	cmp	x1, x0
  400664:	540000a0 	b.eq	400678 <deregister_tm_clones+0x28>  // b.none
  400668:	90000001 	adrp	x1, 400000 <_init-0x540>
  40066c:	f9464821 	ldr	x1, [x1, #3216]
  400670:	b4000041 	cbz	x1, 400678 <deregister_tm_clones+0x28>
  400674:	d61f0020 	br	x1
  400678:	d65f03c0 	ret
  40067c:	d503201f 	nop

0000000000400680 <register_tm_clones>:
  400680:	b0000080 	adrp	x0, 411000 <__libc_start_main@GLIBC_2.17>
  400684:	91012000 	add	x0, x0, #0x48
  400688:	b0000081 	adrp	x1, 411000 <__libc_start_main@GLIBC_2.17>
  40068c:	91012021 	add	x1, x1, #0x48
  400690:	cb000021 	sub	x1, x1, x0
  400694:	9343fc21 	asr	x1, x1, #3
  400698:	8b41fc21 	add	x1, x1, x1, lsr #63
  40069c:	9341fc21 	asr	x1, x1, #1
  4006a0:	b40000a1 	cbz	x1, 4006b4 <register_tm_clones+0x34>
  4006a4:	90000002 	adrp	x2, 400000 <_init-0x540>
  4006a8:	f9464c42 	ldr	x2, [x2, #3224]
  4006ac:	b4000042 	cbz	x2, 4006b4 <register_tm_clones+0x34>
  4006b0:	d61f0040 	br	x2
  4006b4:	d65f03c0 	ret

00000000004006b8 <__do_global_dtors_aux>:
  4006b8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006bc:	910003fd 	mov	x29, sp
  4006c0:	f9000bf3 	str	x19, [sp, #16]
  4006c4:	b0000093 	adrp	x19, 411000 <__libc_start_main@GLIBC_2.17>
  4006c8:	39412260 	ldrb	w0, [x19, #72]
  4006cc:	35000080 	cbnz	w0, 4006dc <__do_global_dtors_aux+0x24>
  4006d0:	97ffffe0 	bl	400650 <deregister_tm_clones>
  4006d4:	52800020 	mov	w0, #0x1                   	// #1
  4006d8:	39012260 	strb	w0, [x19, #72]
  4006dc:	f9400bf3 	ldr	x19, [sp, #16]
  4006e0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4006e4:	d65f03c0 	ret

00000000004006e8 <frame_dummy>:
  4006e8:	17ffffe6 	b	400680 <register_tm_clones>

00000000004006ec <dijkstra>:
  4006ec:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  4006f0:	910003fd 	mov	x29, sp
  4006f4:	f9000fa0 	str	x0, [x29, #24]
  4006f8:	b90017a1 	str	w1, [x29, #20]
  4006fc:	52800020 	mov	w0, #0x1                   	// #1
  400700:	b9003fa0 	str	w0, [x29, #60]
  400704:	1400002e 	b	4007bc <dijkstra+0xd0>
  400708:	f9400fa2 	ldr	x2, [x29, #24]
  40070c:	b9803fa3 	ldrsw	x3, [x29, #60]
  400710:	b98017a1 	ldrsw	x1, [x29, #20]
  400714:	aa0103e0 	mov	x0, x1
  400718:	d37ff800 	lsl	x0, x0, #1
  40071c:	8b010000 	add	x0, x0, x1
  400720:	d37ff800 	lsl	x0, x0, #1
  400724:	8b030000 	add	x0, x0, x3
  400728:	b8607842 	ldr	w2, [x2, x0, lsl #2]
  40072c:	f9400fa0 	ldr	x0, [x29, #24]
  400730:	b9803fa1 	ldrsw	x1, [x29, #60]
  400734:	91009021 	add	x1, x1, #0x24
  400738:	b8217802 	str	w2, [x0, x1, lsl #2]
  40073c:	f9400fa0 	ldr	x0, [x29, #24]
  400740:	b9803fa1 	ldrsw	x1, [x29, #60]
  400744:	9100c021 	add	x1, x1, #0x30
  400748:	b821781f 	str	wzr, [x0, x1, lsl #2]
  40074c:	b9403fa1 	ldr	w1, [x29, #60]
  400750:	b94017a0 	ldr	w0, [x29, #20]
  400754:	6b00003f 	cmp	w1, w0
  400758:	54000200 	b.eq	400798 <dijkstra+0xac>  // b.none
  40075c:	f9400fa0 	ldr	x0, [x29, #24]
  400760:	b9803fa1 	ldrsw	x1, [x29, #60]
  400764:	91009021 	add	x1, x1, #0x24
  400768:	b8617801 	ldr	w1, [x0, x1, lsl #2]
  40076c:	528fffc0 	mov	w0, #0x7ffe                	// #32766
  400770:	6b00003f 	cmp	w1, w0
  400774:	5400012c 	b.gt	400798 <dijkstra+0xac>
  400778:	f9400fa1 	ldr	x1, [x29, #24]
  40077c:	b9803fa0 	ldrsw	x0, [x29, #60]
  400780:	9100a000 	add	x0, x0, #0x28
  400784:	d37ef400 	lsl	x0, x0, #2
  400788:	8b000020 	add	x0, x1, x0
  40078c:	b94017a1 	ldr	w1, [x29, #20]
  400790:	b9000801 	str	w1, [x0, #8]
  400794:	14000007 	b	4007b0 <dijkstra+0xc4>
  400798:	f9400fa1 	ldr	x1, [x29, #24]
  40079c:	b9803fa0 	ldrsw	x0, [x29, #60]
  4007a0:	9100a000 	add	x0, x0, #0x28
  4007a4:	d37ef400 	lsl	x0, x0, #2
  4007a8:	8b000020 	add	x0, x1, x0
  4007ac:	b900081f 	str	wzr, [x0, #8]
  4007b0:	b9403fa0 	ldr	w0, [x29, #60]
  4007b4:	11000400 	add	w0, w0, #0x1
  4007b8:	b9003fa0 	str	w0, [x29, #60]
  4007bc:	b9403fa0 	ldr	w0, [x29, #60]
  4007c0:	7100141f 	cmp	w0, #0x5
  4007c4:	54fffa2d 	b.le	400708 <dijkstra+0x1c>
  4007c8:	f9400fa0 	ldr	x0, [x29, #24]
  4007cc:	b98017a1 	ldrsw	x1, [x29, #20]
  4007d0:	9100c021 	add	x1, x1, #0x30
  4007d4:	52800022 	mov	w2, #0x1                   	// #1
  4007d8:	b8217802 	str	w2, [x0, x1, lsl #2]
  4007dc:	f9400fa0 	ldr	x0, [x29, #24]
  4007e0:	b98017a1 	ldrsw	x1, [x29, #20]
  4007e4:	91009021 	add	x1, x1, #0x24
  4007e8:	b821781f 	str	wzr, [x0, x1, lsl #2]
  4007ec:	52800020 	mov	w0, #0x1                   	// #1
  4007f0:	b9003fa0 	str	w0, [x29, #60]
  4007f4:	14000072 	b	4009bc <dijkstra+0x2d0>
  4007f8:	528fffe0 	mov	w0, #0x7fff                	// #32767
  4007fc:	b90033a0 	str	w0, [x29, #48]
  400800:	b94017a0 	ldr	w0, [x29, #20]
  400804:	b9002fa0 	str	w0, [x29, #44]
  400808:	52800020 	mov	w0, #0x1                   	// #1
  40080c:	b9003ba0 	str	w0, [x29, #56]
  400810:	14000018 	b	400870 <dijkstra+0x184>
  400814:	f9400fa0 	ldr	x0, [x29, #24]
  400818:	b9803ba1 	ldrsw	x1, [x29, #56]
  40081c:	9100c021 	add	x1, x1, #0x30
  400820:	b8617800 	ldr	w0, [x0, x1, lsl #2]
  400824:	7100001f 	cmp	w0, #0x0
  400828:	540001e1 	b.ne	400864 <dijkstra+0x178>  // b.any
  40082c:	f9400fa0 	ldr	x0, [x29, #24]
  400830:	b9803ba1 	ldrsw	x1, [x29, #56]
  400834:	91009021 	add	x1, x1, #0x24
  400838:	b8617800 	ldr	w0, [x0, x1, lsl #2]
  40083c:	b94033a1 	ldr	w1, [x29, #48]
  400840:	6b00003f 	cmp	w1, w0
  400844:	5400010d 	b.le	400864 <dijkstra+0x178>
  400848:	b9403ba0 	ldr	w0, [x29, #56]
  40084c:	b9002fa0 	str	w0, [x29, #44]
  400850:	f9400fa0 	ldr	x0, [x29, #24]
  400854:	b9803ba1 	ldrsw	x1, [x29, #56]
  400858:	91009021 	add	x1, x1, #0x24
  40085c:	b8617800 	ldr	w0, [x0, x1, lsl #2]
  400860:	b90033a0 	str	w0, [x29, #48]
  400864:	b9403ba0 	ldr	w0, [x29, #56]
  400868:	11000400 	add	w0, w0, #0x1
  40086c:	b9003ba0 	str	w0, [x29, #56]
  400870:	b9403ba0 	ldr	w0, [x29, #56]
  400874:	7100141f 	cmp	w0, #0x5
  400878:	54fffced 	b.le	400814 <dijkstra+0x128>
  40087c:	f9400fa0 	ldr	x0, [x29, #24]
  400880:	b9802fa1 	ldrsw	x1, [x29, #44]
  400884:	9100c021 	add	x1, x1, #0x30
  400888:	52800022 	mov	w2, #0x1                   	// #1
  40088c:	b8217802 	str	w2, [x0, x1, lsl #2]
  400890:	52800020 	mov	w0, #0x1                   	// #1
  400894:	b9002ba0 	str	w0, [x29, #40]
  400898:	14000043 	b	4009a4 <dijkstra+0x2b8>
  40089c:	f9400fa0 	ldr	x0, [x29, #24]
  4008a0:	b9802ba1 	ldrsw	x1, [x29, #40]
  4008a4:	9100c021 	add	x1, x1, #0x30
  4008a8:	b8617800 	ldr	w0, [x0, x1, lsl #2]
  4008ac:	7100001f 	cmp	w0, #0x0
  4008b0:	54000741 	b.ne	400998 <dijkstra+0x2ac>  // b.any
  4008b4:	f9400fa2 	ldr	x2, [x29, #24]
  4008b8:	b9802ba3 	ldrsw	x3, [x29, #40]
  4008bc:	b9802fa1 	ldrsw	x1, [x29, #44]
  4008c0:	aa0103e0 	mov	x0, x1
  4008c4:	d37ff800 	lsl	x0, x0, #1
  4008c8:	8b010000 	add	x0, x0, x1
  4008cc:	d37ff800 	lsl	x0, x0, #1
  4008d0:	8b030000 	add	x0, x0, x3
  4008d4:	b8607841 	ldr	w1, [x2, x0, lsl #2]
  4008d8:	528fffc0 	mov	w0, #0x7ffe                	// #32766
  4008dc:	6b00003f 	cmp	w1, w0
  4008e0:	540005cc 	b.gt	400998 <dijkstra+0x2ac>
  4008e4:	f9400fa0 	ldr	x0, [x29, #24]
  4008e8:	b9802fa1 	ldrsw	x1, [x29, #44]
  4008ec:	91009021 	add	x1, x1, #0x24
  4008f0:	b8617802 	ldr	w2, [x0, x1, lsl #2]
  4008f4:	f9400fa3 	ldr	x3, [x29, #24]
  4008f8:	b9802ba4 	ldrsw	x4, [x29, #40]
  4008fc:	b9802fa1 	ldrsw	x1, [x29, #44]
  400900:	aa0103e0 	mov	x0, x1
  400904:	d37ff800 	lsl	x0, x0, #1
  400908:	8b010000 	add	x0, x0, x1
  40090c:	d37ff800 	lsl	x0, x0, #1
  400910:	8b040000 	add	x0, x0, x4
  400914:	b8607860 	ldr	w0, [x3, x0, lsl #2]
  400918:	0b000041 	add	w1, w2, w0
  40091c:	f9400fa0 	ldr	x0, [x29, #24]
  400920:	b9802ba2 	ldrsw	x2, [x29, #40]
  400924:	91009042 	add	x2, x2, #0x24
  400928:	b8627800 	ldr	w0, [x0, x2, lsl #2]
  40092c:	6b00003f 	cmp	w1, w0
  400930:	5400034a 	b.ge	400998 <dijkstra+0x2ac>  // b.tcont
  400934:	f9400fa0 	ldr	x0, [x29, #24]
  400938:	b9802fa1 	ldrsw	x1, [x29, #44]
  40093c:	91009021 	add	x1, x1, #0x24
  400940:	b8617802 	ldr	w2, [x0, x1, lsl #2]
  400944:	f9400fa3 	ldr	x3, [x29, #24]
  400948:	b9802ba4 	ldrsw	x4, [x29, #40]
  40094c:	b9802fa1 	ldrsw	x1, [x29, #44]
  400950:	aa0103e0 	mov	x0, x1
  400954:	d37ff800 	lsl	x0, x0, #1
  400958:	8b010000 	add	x0, x0, x1
  40095c:	d37ff800 	lsl	x0, x0, #1
  400960:	8b040000 	add	x0, x0, x4
  400964:	b8607860 	ldr	w0, [x3, x0, lsl #2]
  400968:	0b000042 	add	w2, w2, w0
  40096c:	f9400fa0 	ldr	x0, [x29, #24]
  400970:	b9802ba1 	ldrsw	x1, [x29, #40]
  400974:	91009021 	add	x1, x1, #0x24
  400978:	b8217802 	str	w2, [x0, x1, lsl #2]
  40097c:	f9400fa1 	ldr	x1, [x29, #24]
  400980:	b9802ba0 	ldrsw	x0, [x29, #40]
  400984:	9100a000 	add	x0, x0, #0x28
  400988:	d37ef400 	lsl	x0, x0, #2
  40098c:	8b000020 	add	x0, x1, x0
  400990:	b9402fa1 	ldr	w1, [x29, #44]
  400994:	b9000801 	str	w1, [x0, #8]
  400998:	b9402ba0 	ldr	w0, [x29, #40]
  40099c:	11000400 	add	w0, w0, #0x1
  4009a0:	b9002ba0 	str	w0, [x29, #40]
  4009a4:	b9402ba0 	ldr	w0, [x29, #40]
  4009a8:	7100141f 	cmp	w0, #0x5
  4009ac:	54fff78d 	b.le	40089c <dijkstra+0x1b0>
  4009b0:	b9403fa0 	ldr	w0, [x29, #60]
  4009b4:	11000400 	add	w0, w0, #0x1
  4009b8:	b9003fa0 	str	w0, [x29, #60]
  4009bc:	b9403fa0 	ldr	w0, [x29, #60]
  4009c0:	7100101f 	cmp	w0, #0x4
  4009c4:	54fff1ad 	b.le	4007f8 <dijkstra+0x10c>
  4009c8:	52800020 	mov	w0, #0x1                   	// #1
  4009cc:	b9003fa0 	str	w0, [x29, #60]
  4009d0:	1400002a 	b	400a78 <dijkstra+0x38c>
  4009d4:	b9403fa1 	ldr	w1, [x29, #60]
  4009d8:	b94017a0 	ldr	w0, [x29, #20]
  4009dc:	6b00003f 	cmp	w1, w0
  4009e0:	54000460 	b.eq	400a6c <dijkstra+0x380>  // b.none
  4009e4:	f9400fa0 	ldr	x0, [x29, #24]
  4009e8:	b9803fa1 	ldrsw	x1, [x29, #60]
  4009ec:	91009021 	add	x1, x1, #0x24
  4009f0:	b8617801 	ldr	w1, [x0, x1, lsl #2]
  4009f4:	90000000 	adrp	x0, 400000 <_init-0x540>
  4009f8:	91328000 	add	x0, x0, #0xca0
  4009fc:	b9403fa3 	ldr	w3, [x29, #60]
  400a00:	2a0103e2 	mov	w2, w1
  400a04:	b9403fa1 	ldr	w1, [x29, #60]
  400a08:	97fffef2 	bl	4005d0 <printf@plt>
  400a0c:	f9400fa1 	ldr	x1, [x29, #24]
  400a10:	b9803fa0 	ldrsw	x0, [x29, #60]
  400a14:	9100a000 	add	x0, x0, #0x28
  400a18:	d37ef400 	lsl	x0, x0, #2
  400a1c:	8b000020 	add	x0, x1, x0
  400a20:	b9400800 	ldr	w0, [x0, #8]
  400a24:	b90037a0 	str	w0, [x29, #52]
  400a28:	1400000c 	b	400a58 <dijkstra+0x36c>
  400a2c:	90000000 	adrp	x0, 400000 <_init-0x540>
  400a30:	91330000 	add	x0, x0, #0xcc0
  400a34:	b94037a1 	ldr	w1, [x29, #52]
  400a38:	97fffee6 	bl	4005d0 <printf@plt>
  400a3c:	f9400fa1 	ldr	x1, [x29, #24]
  400a40:	b98037a0 	ldrsw	x0, [x29, #52]
  400a44:	9100a000 	add	x0, x0, #0x28
  400a48:	d37ef400 	lsl	x0, x0, #2
  400a4c:	8b000020 	add	x0, x1, x0
  400a50:	b9400800 	ldr	w0, [x0, #8]
  400a54:	b90037a0 	str	w0, [x29, #52]
  400a58:	b94037a0 	ldr	w0, [x29, #52]
  400a5c:	7100001f 	cmp	w0, #0x0
  400a60:	54fffe61 	b.ne	400a2c <dijkstra+0x340>  // b.any
  400a64:	52800140 	mov	w0, #0xa                   	// #10
  400a68:	97fffede 	bl	4005e0 <putchar@plt>
  400a6c:	b9403fa0 	ldr	w0, [x29, #60]
  400a70:	11000400 	add	w0, w0, #0x1
  400a74:	b9003fa0 	str	w0, [x29, #60]
  400a78:	b9403fa0 	ldr	w0, [x29, #60]
  400a7c:	7100141f 	cmp	w0, #0x5
  400a80:	54fffaad 	b.le	4009d4 <dijkstra+0x2e8>
  400a84:	d503201f 	nop
  400a88:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400a8c:	d65f03c0 	ret

0000000000400a90 <main>:
  400a90:	a9b07bfd 	stp	x29, x30, [sp, #-256]!
  400a94:	910003fd 	mov	x29, sp
  400a98:	52800020 	mov	w0, #0x1                   	// #1
  400a9c:	b9001fa0 	str	w0, [x29, #28]
  400aa0:	1400002b 	b	400b4c <main+0xbc>
  400aa4:	52800020 	mov	w0, #0x1                   	// #1
  400aa8:	b9001ba0 	str	w0, [x29, #24]
  400aac:	14000022 	b	400b34 <main+0xa4>
  400ab0:	b9401fa1 	ldr	w1, [x29, #28]
  400ab4:	b9401ba0 	ldr	w0, [x29, #24]
  400ab8:	6b00003f 	cmp	w1, w0
  400abc:	540001c1 	b.ne	400af4 <main+0x64>  // b.any
  400ac0:	b9401fa0 	ldr	w0, [x29, #28]
  400ac4:	b9401ba1 	ldr	w1, [x29, #24]
  400ac8:	93407c22 	sxtw	x2, w1
  400acc:	93407c01 	sxtw	x1, w0
  400ad0:	aa0103e0 	mov	x0, x1
  400ad4:	d37ff800 	lsl	x0, x0, #1
  400ad8:	8b010000 	add	x0, x0, x1
  400adc:	d37ff800 	lsl	x0, x0, #1
  400ae0:	8b020000 	add	x0, x0, x2
  400ae4:	d37ef400 	lsl	x0, x0, #2
  400ae8:	910083a1 	add	x1, x29, #0x20
  400aec:	b820683f 	str	wzr, [x1, x0]
  400af0:	1400000e 	b	400b28 <main+0x98>
  400af4:	b9401fa0 	ldr	w0, [x29, #28]
  400af8:	b9401ba1 	ldr	w1, [x29, #24]
  400afc:	93407c22 	sxtw	x2, w1
  400b00:	93407c01 	sxtw	x1, w0
  400b04:	aa0103e0 	mov	x0, x1
  400b08:	d37ff800 	lsl	x0, x0, #1
  400b0c:	8b010000 	add	x0, x0, x1
  400b10:	d37ff800 	lsl	x0, x0, #1
  400b14:	8b020000 	add	x0, x0, x2
  400b18:	d37ef400 	lsl	x0, x0, #2
  400b1c:	910083a1 	add	x1, x29, #0x20
  400b20:	528fffe2 	mov	w2, #0x7fff                	// #32767
  400b24:	b8206822 	str	w2, [x1, x0]
  400b28:	b9401ba0 	ldr	w0, [x29, #24]
  400b2c:	11000400 	add	w0, w0, #0x1
  400b30:	b9001ba0 	str	w0, [x29, #24]
  400b34:	b9401ba0 	ldr	w0, [x29, #24]
  400b38:	7100141f 	cmp	w0, #0x5
  400b3c:	54fffbad 	b.le	400ab0 <main+0x20>
  400b40:	b9401fa0 	ldr	w0, [x29, #28]
  400b44:	11000400 	add	w0, w0, #0x1
  400b48:	b9001fa0 	str	w0, [x29, #28]
  400b4c:	b9401fa0 	ldr	w0, [x29, #28]
  400b50:	7100141f 	cmp	w0, #0x5
  400b54:	54fffa8d 	b.le	400aa4 <main+0x14>
  400b58:	52800020 	mov	w0, #0x1                   	// #1
  400b5c:	b900ffa0 	str	w0, [x29, #252]
  400b60:	1400001a 	b	400bc8 <main+0x138>
  400b64:	90000000 	adrp	x0, 400000 <_init-0x540>
  400b68:	91334000 	add	x0, x0, #0xcd0
  400b6c:	97fffe91 	bl	4005b0 <puts@plt>
  400b70:	910053a3 	add	x3, x29, #0x14
  400b74:	910063a2 	add	x2, x29, #0x18
  400b78:	910073a1 	add	x1, x29, #0x1c
  400b7c:	90000000 	adrp	x0, 400000 <_init-0x540>
  400b80:	9133e000 	add	x0, x0, #0xcf8
  400b84:	97fffe8f 	bl	4005c0 <__isoc99_scanf@plt>
  400b88:	b9401fa0 	ldr	w0, [x29, #28]
  400b8c:	b9401ba1 	ldr	w1, [x29, #24]
  400b90:	b94017a2 	ldr	w2, [x29, #20]
  400b94:	93407c23 	sxtw	x3, w1
  400b98:	93407c01 	sxtw	x1, w0
  400b9c:	aa0103e0 	mov	x0, x1
  400ba0:	d37ff800 	lsl	x0, x0, #1
  400ba4:	8b010000 	add	x0, x0, x1
  400ba8:	d37ff800 	lsl	x0, x0, #1
  400bac:	8b030000 	add	x0, x0, x3
  400bb0:	d37ef400 	lsl	x0, x0, #2
  400bb4:	910083a1 	add	x1, x29, #0x20
  400bb8:	b8206822 	str	w2, [x1, x0]
  400bbc:	b940ffa0 	ldr	w0, [x29, #252]
  400bc0:	11000400 	add	w0, w0, #0x1
  400bc4:	b900ffa0 	str	w0, [x29, #252]
  400bc8:	b940ffa0 	ldr	w0, [x29, #252]
  400bcc:	7100241f 	cmp	w0, #0x9
  400bd0:	54fffcad 	b.le	400b64 <main+0xd4>
  400bd4:	910083a0 	add	x0, x29, #0x20
  400bd8:	52800021 	mov	w1, #0x1                   	// #1
  400bdc:	97fffec4 	bl	4006ec <dijkstra>
  400be0:	d503201f 	nop
  400be4:	a8d07bfd 	ldp	x29, x30, [sp], #256
  400be8:	d65f03c0 	ret
  400bec:	00000000 	.inst	0x00000000 ; undefined

0000000000400bf0 <__libc_csu_init>:
  400bf0:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400bf4:	910003fd 	mov	x29, sp
  400bf8:	a901d7f4 	stp	x20, x21, [sp, #24]
  400bfc:	90000094 	adrp	x20, 410000 <__FRAME_END__+0xf2fc>
  400c00:	90000095 	adrp	x21, 410000 <__FRAME_END__+0xf2fc>
  400c04:	91374294 	add	x20, x20, #0xdd0
  400c08:	913722b5 	add	x21, x21, #0xdc8
  400c0c:	a902dff6 	stp	x22, x23, [sp, #40]
  400c10:	cb150294 	sub	x20, x20, x21
  400c14:	f9001ff8 	str	x24, [sp, #56]
  400c18:	2a0003f6 	mov	w22, w0
  400c1c:	aa0103f7 	mov	x23, x1
  400c20:	9343fe94 	asr	x20, x20, #3
  400c24:	aa0203f8 	mov	x24, x2
  400c28:	97fffe46 	bl	400540 <_init>
  400c2c:	b4000194 	cbz	x20, 400c5c <__libc_csu_init+0x6c>
  400c30:	f9000bb3 	str	x19, [x29, #16]
  400c34:	d2800013 	mov	x19, #0x0                   	// #0
  400c38:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400c3c:	aa1803e2 	mov	x2, x24
  400c40:	aa1703e1 	mov	x1, x23
  400c44:	2a1603e0 	mov	w0, w22
  400c48:	91000673 	add	x19, x19, #0x1
  400c4c:	d63f0060 	blr	x3
  400c50:	eb13029f 	cmp	x20, x19
  400c54:	54ffff21 	b.ne	400c38 <__libc_csu_init+0x48>  // b.any
  400c58:	f9400bb3 	ldr	x19, [x29, #16]
  400c5c:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400c60:	a942dff6 	ldp	x22, x23, [sp, #40]
  400c64:	f9401ff8 	ldr	x24, [sp, #56]
  400c68:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400c6c:	d65f03c0 	ret

0000000000400c70 <__libc_csu_fini>:
  400c70:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400c74 <_fini>:
  400c74:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400c78:	910003fd 	mov	x29, sp
  400c7c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400c80:	d65f03c0 	ret
